In the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop.
a) Moore machine
b) Meally machine
c) Johnson counter
d) Ring counter
A divide-by-50 counter divides the input signal to a 1 Hz signal.
a) 10 Hz
b) 50 Hz
c) 100 Hz
d) 500 Hz
A negative edge-triggered flip-flop changes its state when?
a) Enable input (EN) is set
b) Preset input (PRE) is set
c) Low-to-high transition of
d) High-to-low transition of clock
In asynchronous digital systems all the circuits change their state with respect to a common clock?
a) True
b) False
c) Both
d) None
De-multiplexer converts…..data to…data
a) Parallel data, serial data
b) Serial data, parallel data
c) Encoded data, decoded data
d) All of the given options
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
a) A > B = 1, A < B = 1, A < B = 1
b) A > B = 0, A < B = 1, A = B = 0
c) A > B = 1, A < B = 0, A = B = 0
d) A > B = 0, A < B = 1, A = B = 1
