For a positive edge-Triggered J-K Flip-Flop with both J and K High, the output will……. if the clock goes HIGH?
a) toggle
b) set
c) reset
d) not change
The storage cell in SRAM is?
a) a flip-flop
b) a capacitor
c) a fuse
d) a magnetic domain
The 4-bit 2''s complement representation of "+5" is……
a) 1010
b) 1110
c) 1011
d) 0101
AGAL is essentially a…………..
a) Non-reprogrammable PAL
b) PAL that is programmed only by the manufacturer
c) Very large PAL
d) Reprogrammable PAL
The alternate solution for a de-multiplexer-register combination circuit is_
a) Parallel in/Serial out shift register
b) Serial in / Parallel out shift register
c) Parallel in/Parallel out shift register
d) Serial in/Serial Out shift register
A synchronous decade counter will have flip-flops?
a) 3
b) 4
c) 7
d) 10
