The divide-by-60 counter in digital clock is implemented by using two cascading counters:
a) Mod-6, Mod-10
b) Mod-50, Mod-10
c) Mod-10, Mod-50
d) Mod-50, Mod-6
In a sequential circuit the next state is determined by…… and……..?
a) State variable, current state
b) Current state, flip-flop output
c) Current state and external input
d) Input and clock signal applied
The minimum time for which the input signal has to be maintained at the input of flip-flop is called………of the flip-flop.
a) Set-up time
b) Hold time
c) Pulse Interval time
d) Pulse Stability time (PST)
A 8-bit serial in / parallel out shift register contains the value “8”,… clock signal(s) will be required to shift the value completely out of the register.
a) 1
b) 2
c) 4
d) 8
