Three cascaded modulus-10 counters have an overall modulus of?
a) 30
b) 100
c) 1000
d) 0000
Divide-by-160 counter is achieved by using?
a) Flip-Flop and DIV 10
b) Flip-Flop and DIV 16
c) DIV 16 and DIV 32
d) DIV 16 and DIV 10
A flip-flop is presently in SET state and must remain SET on the
next clock pulse. What must J and K be?
a) J=1, K=0
b) = 1, KX(Don't care)
c)J = X(Don't care), K=0
d) J=0, K = X(Don't care)
For a gated D-Latch if EN=1 and D=1 then Q(t+1)= ……………
a) 0
b) 1
c) Q(t)
d) Invalid
A decade counter can be implemented by truncating the counting sequence of a MOD-20 counter?
a) True
b) False
c) Both
d) None
In case of cascading Integrated Circuit counters, the enable inputs and RCOof the Integrated Circuit counters allow cascading of multiple counters together?
a) True
b) False
c) Both
d) None
